This invention relates to a digital phase control method and a digital phase control circuit and, more particularly, to technique for phase shifting a predetermined number of clock signals having the same frequency and having different phases with high precision and high resolution as a whole with those phase intervals maintained to keep a predetermined interval.
Actually, in fields of multi-communications and recording/reproducing of information, a request has been made as regards techniques for phase shifting a predetermined number of clock signals (multi-phase clock signals) having the same frequency and having different phases with high precision and at high resolution as a whole with those phase intervals maintained to keep a predetermined interval.
In digital transmission of data, bit synchronization using the multi-phase clock signals is carried out on extracting and reproducing a received data signal. In this event, there is not only a method of controlling a selection circuit for selecting one clock signal from the multi-phase clock signals but also a method of synchronizing the multi-phase clock signals to a data signal by phase controlling (phase shifting) all of the multi-phase clock signals.
As one of conventional phase control methods, a phase interpolation method is known in the art. The phase interpolation method is a method of synthesizing given two clock signals having different phases to produce a synthesized clock signal having a phase between the different phases of the two clock signals.
In the manner which will later be described in conjunction with FIGS. 2 and 3, a conventional phase interpolator generally comprises a core portion and a filter portion. According to the phase interpolate method, it is possible to carry out digital phase control at high resolution.
However, problems arise in the digital phase control according to the above-mentioned phase interpolation method as follows.
It is necessary for the above-mentioned phase interpolation method to use clock signals having four phases of 0xc2x0, 90xc2x0, 180xc2x0, and 270xc2x0. In a case of applying the phase interpolation method to the phase control for the multi-phase clock signals, increase in consumed power and circuit""s scale are problems.
In addition, the above-mentioned phase interpolation method is suitable to phase control a clock signal having one phase with high precision because the phase interpolation method is for phase controlling the clock signal having one phase. Now, the phase interpolation method does not guarantee in principle that the phase intervals of the multi-phase clock signals are maintained with high precision.
Furthermore, inasmuch as the above-mentioned phase interpolation method regards, as a sine wave, the clock signal which is a rectangular wave in practice on the basis of a principle such that xe2x80x9ca sine wave having any phase is obtained by multiplying two sine waves weighted and adding themxe2x80x9d, a clock signal in theory is not synthesized and distortion occurs in a synthesized wave. As a result, it is difficult to synthesize the clock signal so as to stand practically.
It is therefore an object of this invention to provide a digital phase control method and a digital phase control circuit which are capable of phase shifting a predetermined number of clock signals having the same frequency and having different phases with high precision and at high resolution as a whole with those phase intervals maintained to keep a predetermined interval.
It is another object of this invention to provide a digital phase control circuit of the type described, which is capable of realizing such a digital phase control circuit with a low consumed power and with a small circuit""s scale.
It is still another object of this invention to provide a digital phase control method and a digital phase control circuit which are capable of generating a clock signal of high quality with a well-ordered wave.
It is yet another object of this invention to provide a digital phase control method and a digital phase control circuit which are capable of giving full play to performance upon normal design.
Other objects of this invention will become clear as the description proceeds.
According to a first aspect of this invention, a digital phase control method comprises the steps of preparing first multi-phase clock signals having a fixed phase and having a first equal phase interval, of preparing second multi-phase clock signals having a second equal phase interval different from the first equal phase interval, of phase locking a specific clock signal in the first multi-phase clock signals and a particular clock signal in the second multi-phase clock signals, and of changing a combination of the specific and the particular clock signals to be phase-locked to shift a phase of the second multi-phase clock signals.
Among through the specification, a xe2x80x9cphase intervalxe2x80x9d means a phase difference between two adjacent clock signals among multi-phase clock signals. The multi-phase clock signals having an equal phase interval may be generated by using, for example, an analog delay locked loop (DLL). In addition, the xe2x80x9cmulti-phase clock signalsxe2x80x9d mean a predetermined number of clock signals having the same frequency and having different phases.
According to a second aspect of this invention, a digital phase control method comprising the steps of generating first multi-phase clock signals having a fixed phase and having a first equal phase interval using a first delay line comprising a plurality of primary delay buffers which are chained with each other, of selecting one of the first multi-phase clock signal to pick up a selected clock signal, and of supplying the selected clock signal to one of secondary delay buffers chained with each other in a second delay line to generate second multi-phase clock signals having a second equal phase interval different from the first equal phase interval using the second delay line.
In the digital phase control method according to the second aspect of this invention, the secondary delay buffers of the second delay line may be chained with each other in a ring-shaped fashion. In addition, the first delay line may be feedback controlled by a first delay locked loop and said second delay line may be feedback controlled by a second delay locked loop.
According to a third aspect of this invention, a digital phase control circuit comprises a first delay line comprising M primary delay buffers which are chained with each other where M represents a first positive integer which is not less than two. The first delay line is feedback controlled by a first delay locked loop to produce first through M-th primary delay output signals. A delay buffer train comprises N or more secondary delay buffers which are chained with each other where N represents a second positive integer which is not less than two and which is different from the first positive integer M. A first selection circuit selects one of the first through the M-th primary delay output signals as a selected primary delay output signal. A second selection circuit selects one of the N or more secondary delay buffers as a first stage of a second delay line in the delay buffer train to supply the selected primary delay output signal to the first stage. The second delay line comprises N successive secondary delay buffers having a first one of the N successive secondary delay buffers as the first stage. A second delay locked loop feedback controls the second delay line.
In the digital phase control circuit according to the third aspect of this invention, the N or more secondary delay buffers of the delay buffer train may be chained with each other in a ring-shaped fashion. In addition, each of the M primary delay buffers and the N or more secondary delay buffers may have a single-phase configuration or may have a differential configuration. In the differential configuration, the first delay line produces first though M-th primary differential clock signal pairs as the first through the M-th primary delay output signals and the first selection circuit produces a selected primary differential clock pair as the selected primary delay output signal. The digital phase control circuit further may comprise a switching circuit for switching inversion and non-inversion of the selected primary differential clock pair.
According to a fourth aspect of this invention, a digital phase control circuit comprises a first delay line comprising M primary delay buffers which are chained with each other where M represents a first positive integer which is not less than two. The first delay line is feedback controlled by a first delay locked loop to produce first through M-th primary delay output signals. A delay buffer train comprising N secondary delay buffers which are chained with each other in a ring-shaped fashion where N represents a second positive integer which is not less than two and which is different from the first positive integer M. N first-stage delay buffers have outputs connected between respective adjacent two of the N secondary delay buffers. Each of the N first-stage delay buffers has similar characteristics of each of the N secondary delay buffers. A first selection circuit selects one of the first through the M-th primary delay output signals as a selected primary delay output signal. Connected to inputs of the N first-stage delay buffers in parallel, a second selection circuit selects one of the N first-stage delay buffers as a selected first-stage delay buffer of a second delay line to supply the selected primary delay output signal to the selected first-stage delay buffer. The second delay line comprises the selected first-stage delay buffer and (N-1) successive secondary delay buffers following the selected first-stage delay buffer. A second delay locked loop feedback controls the second delay line.
In the digital phase control circuit according to the fourth aspect of this invention, each of the M primary delay buffers, the N secondary delay buffers, and the N first-stage delay buffers may have a single-phase configuration or a differential configuration. In the differential configuration, the first delay line produces first though M-th primary differential clock signal pairs as the first through the M-th primary delay output signals, and the first selection circuit produces a selected primary differential clock pair as the selected primary delay output signal. The digital phase control circuit further may comprise a switching circuit for switching inversion and non-inversion of the selected primary differential clock signal pair to produce a passed primary differential clock signal pair which is supplied to the second selection circuit.
According to a fifth aspect of this invention, a delay locked loop comprises a delay buffer train comprising a plurality of delay buffers which are chained with each other in a ring-shaped fashion and means for configuring a delay line comprising one of the delay buffers or successive delay buffers.
According to a sixth aspect of this invention, a delay locked loop comprises a delay buffer train comprising a plurality of delay buffers which are chained with each other in a ring-shaped fashion, means for activating a delay line comprising a predetermined number of the delay buffers which circulate in the delay buffer train in position, and means for detecting a phase difference between an input signal and an output signal of the delay line to feedback control the delay line.
According to a seventh aspect of this invention, a delay locked loop comprises a delay buffer train comprising a plurality of delay buffers which are chained with each other in a ring-shaped fashion, a selection circuit for selecting one of the delay buffer as a selected delay buffer to be first supplied with a clock signal, and means for feedback controlling a delay line comprising the selected delay buffer and successive delay buffers following the selected delay buffer in the delay buffer train.
In the delay locked loop according to each of the fifth through the seventh aspects of this invention, the delay locked loop further may comprise means for cutting off propagation of a signal flowing in the delay buffer train.